The present invention relates to a method of reducing the conductivity (or charge) of a doped semiconductor. The method may be conveniently used in a number of applications. For example, the method may be used to effectively perform the channel or gate recess etches commonly used in Metal Semiconductor Field Effect Transistor (MESFET) devices and High Electron Mobility Transistor (HEMT) devices, including Pseudomorphic High Electron Mobility transistor (PHEMT) devices. The method may also be used to reduce the extrinsic base-collector capacitance in a semiconductor device As such the present invention also relates to devices manufactured according to this method.
A prior art HEMT device will now be described with reference to FIGS. 1A-1G. FIG. 1A depicts a substrate 10 having a buffer layer 11 disposed thereon which in turn has a channel layer 12 disposed thereon. On the channel layer is disposed a Schottky layer 13 and a contact layer 14 is formed on top of the Schottky layer. Each of these layers are conventional epitaxial layers formed by methods known in the prior art. Additionally, these layers are generally formed of semiconductor materials from groups III and V of the Periodic Table of Elements and their alloys. Semiconductor materials such as Gallium Arsenide (GaAs), Indium Phosphide (InP), and Aluminum Gallium Arsenide (AlGaAs), Indium Gallium Arsenide (InGaAs), Indium Aluminum Arsenide (InAlAs) are typically used in such devices. Since the alloys which are used and their level of dopings are known in the prior art, they are not described further here.
In order to form a field effect device in the structure shown in FIG. 1A, metal source and drain contacts 15 and 16 are formed on contact layer 14 (see FIG. 1C). This can be done by patterning a layer of photoresist 17, covering the patterned photoresist with metal 18 and, thereafter, lifting off the photoresist and the layer of metal disposed on top thereof in order to arrive at the structure shown in FIG. 1C. Those skilled in the art will realize, of course, that there are other ways of forming the source contact 15 and drain contact 16 shown in FIG. 1C.
Thereafter, another layer of photoresist 19 is applied and patterned as shown in FIG. 1D to expose an area 20 between the source contact 15 and the drain contact 16. The device is then etched with an etchant suitable to remove the exposed contact layer in area 20. This etch is called a gate recess etch. After the photoresist layer 19 is removed the structure shown in FIG. 1E results.
Sometimes HEMT, PHEMT and MESFET devices are subjected to a second etch. If a second etch is used, the structure of FIG. 1E is covered with a photoresist which is patterned to form a region in the exposed portion 20 of Schottky layer 13 as shown in FIG. 1F. The Schottky layer is subjected to a controlled etch which is called a channel recess etch. This particular etch is one of the most critical steps in the manufacture of prior art HEMT and PHEMT devices. The most common process used for the gate recess etch previously described with reference to FIGS. 1D and 1E and the channel recess etch previously described with reference to FIG. 1F is typically a wet chemical etch which removes device material to the desired depth in the gate area of the device. Typically, the channel etch is not monitored by depth, but rather by measuring the saturation current flowing from the source contact 15 to the drain contact 16 of exemplary HEMT devices being manufactured in a wafer. In manufacturing these devices, many devices are normally manufactured at the same time on a common semiconductor wafer and the saturation current is measured only for a few exemplary devices being formed on the wafer. Presumably, the devices which are measured are representative of all the devices being manufactured on the wafer. Of course, the exemplary devices may or may not be truly representative of all of the devices. In any event, as a channel recess etch proceeds, etching away the conductive material, the conductivity in the channel decreases and therefore the saturation current decreases. Typically, the measurement of the saturation current and the etch processing do not occur at the same time and therefore usually several cycles of etch processing and measuring are alternatingly utilized until the desired saturation current level is reached. After the channel recess etch has been completed, a gate structure 23 is formed and the patterned photoresist 22 is removed. If the Schottky layer 13 includes Aluminum in the alloy thereof, which is commonly the case, a passivation layer 24 is conventionally applied. It is undesirable to expose Aluminum containing compounds to atmosphere since Aluminum is very reactive and subject to oxidation. The passivation layer 24 helps protect against such oxidation.
It is an object of the present invention to provide a method of manufacturing HEMT-type devices having desired saturation current levels but without exposing Aluminum containing compounds of the Schottky layer 13 to atmosphere.
It is another object of the present invention to provide a method of manufacturing HEMT-type devices having desired saturation current levels but without requiring use of a passivation layer to cover Aluminum containing compounds on the gate area.
In one aspect the present invention provides a method of reducing the conductivity of a layer of a group III-V semiconductor doped with a group IV semiconductor, the group III, IV and V semiconductors each having an atomic number with the atomic number of the group IV semiconductor being larger than the atomic numbers of each of the group III and group V semiconductors. The method comprising the steps of forming a region of SiO2 on the group III-V semiconductor layer; and annealing at least the semiconductor layer and the region of SiO2 at a temperature sufficiently high to cause atoms of the group IV semiconductor to leach from the semiconductor layer into the region of SiO2. The region of SiO2 is optionally removed after the annealing step is performed.
In another aspect, the present invention provides a method of forming a gate region of a semiconductor device such as a PHEMT or a HEMT or a MESFET device. The method includes the steps of (i) forming an layer of semiconductor layer doped with Sn; (ii) forming an region of SiO2 on the semiconductor layer, the region of SiO2 corresponding to the gate region to be formed; (iii) annealing at least the semiconductor layer and the region of SiO2 at a temperature sufficiently high to cause atoms of the Sn dopant to leach from the semiconductor layer into the region of SiO2 and to thereby form a region in said semiconductor layer having a reduced concentration of Sn dopant, the annealing step occurring at a temperature sufficiently low and for a period of time sufficiently short to inhibit significant intermixing between the region of SiO2 and the semiconductor layer; (iv) optionally removing the region of SiO2 after the annealing step is performed; and (v) forming a gate electrode on said semiconductor layer.
In yet another aspect the present invention provides a method of reducing base-collector capacitance of a semiconductor device having layer of a group III-V semiconductor which is doped with a group IV semiconductor. The method includes the steps of: forming a region of SiO2 on the group III-V semiconductor layer; annealing at least the semiconductor layer and the region of SiO2 at a temperature sufficiently high to cause atoms of the group IV semiconductor to leach from at least a region of the group III-V semiconductor layer into the region of SiO2; removing the region of SiO2 after the annealing step is performed; and forming a semiconductor layer defining a base region on the region of the group III-V semiconductor layer from which the IV semiconductor was leached.